Today, functional verification consumes most of the time in the design of layered protocols like OSI Model, PCI Express, etc. As we think of reuse of design components, the reuse of verification ...

The SoC industry needs a reuse-oriented, coverage-driven verification methodology built on the rich semantic support of a standard language. This is the second in a series of four articles outlining a ...

Modeling a verification environment with transactions encompasses many areas, including test bench design and debug, golden model comparison, functional verification between abstraction levels and ...

Standard cell libraries have been a mainstay of chip design for many decades since the inception of logic synthesis and composition methodologies. Cell library IP typically contains Verilog models ...

There’s an old saying about simulation: “It’s all about the need for speed.” Simulation is the core technology for functional verification of semiconductors, and the demand for higher runtime ...

The era of “Internet everywhere” is creating a spectrum of applicationstargeted toward low-power and mixed-signal design,in segments ranging from health care to automotive tocommunications. Meanwhile, ...

Sun's engineers modeled a complex cache-coherence protocol, with parallelism and multi-threading, for a high-performance processor. They also used a commercial formal property-checking tool from ...