SiFive To Integrate Nvidia NVLink Fusion For Next-Gen AI Data Center Chips

SiFive has announced a partnership with Nvidia to integrate Nvidia’s NVLink Fusion interconnect technology into its ...
DatacenterDynamics

RISC-V chipmaker SiFive to integrate Nvidia NVLink Fusion into its future chip designs

RISC-V chipmaker SiFive has announced it will integrate Nvidia’s NVLink Fusion interconnect technology with its future ...
Forbes

The RISC-V Architecture Secures Smartwatches With Google And Qualcomm

Today, Google and Qualcomm announced an extension of their partnership to bring RISC-V-based systems-on-chips (SoCs) to market with support for Wear OS, a version of Android for smartwatches and ...

Bolt wants to take on Nvidia by building a RISC-V graphics processor

Bolt Graphics is pressing ahead with its plan to challenge Nvidia and AMD by building a graphics processor around a RISC-V ...
The Register on MSN

Open ISA champ SiFive leaps aboard Nvidia's proprietary interconnect bandwagon

V/NVLink Fusion ... or a bad day for UALink RISC-V champion SiFive has joined a growing number of chip companies by throwing ...
Semiconductor Engineering

Differentiation And Architecture Licenses In RISC‑V

I was discussing with a colleague about the concept of architecture license in RISC-V. I realized that, in the open-source world, it can be a little tricky to grasp. In a traditional processor IP ...
SiliconANGLE

Arm rival SiFive raises $175M to accelerate development of its alternative RISC-V chip architecture

SiFive Inc., a computer chip startup that’s developing processor technology based on the open-source RISC-V instruction set architecture, said today it has raised a hefty $175 million in a late-stage ...
Seeking Alpha

SEALSQ Adopts RISC-V the Open-Standard RISC-V Architecture; Achievement Aligns with Rising Global Demand for Edge-AI and Machine Learning Applications

Geneva, Switzerland, Sept. 13, 2024 (GLOBE NEWSWIRE) -- For more information visit: https://riscv.org/news/2024/07/sealsq-risc-v-semiconductors-is-pioneering ...

Milk-V Titan gives developers a plug-and-play RISC-V desktop

Unlike previous prototypes, which were limited to embedded or experimental use, the Titan targets mainstream usability. Its ...
Electronic Design

Examining the RISC-V Architecture

RISC-V is an open-source instruction set definition managed by RISC-V International. This TechXchange includes content that delves into the architecture and design of a RISC-V processor core. How did ...
Ars Technica

Google wants RISC-V to be a “tier-1” Android architecture

Over the holiday break, the footage from the recent “RISC-V Summit” was posted for the world to see, and would you believe that Google showed up to profess its love for the up-and-coming CPU ...