Delay-inducing defects are causing increasing concern in the semiconductor industry today, particularly at the leading-edge 130- and 90- nanometer nodes. To effectively test for such defects, the ...
As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...
A new technical paper titled “Aging Aware Steepening of the Fault Coverage Curve of a Scan Based Transition Fault Test Set” was published by researchers at Purdue University. “Chip aging may result in ...
The electronics industry is in the midst of a transformation that is drastically changing product design and manufacture. Deep submicron process technology puts more gates on a chip, and the ...
ATPG targets faults at IC-gate boundaries, but 50% of defects are located within cells. Learn how cell-aware ATPG and user-defined fault models help to ferret out these hard-to-squash bugs.
Some results have been hidden because they may be inaccessible to you
Show inaccessible results