Abstract: The paper proposes a proposed 8T SRAM cell design with a read and write path for read and write operations, which improves read and write stability when compared to the 6T SRAM cells. To ...
Abstract: A 15-transistor (15T) SRAM cell-based fully-digital computing-in-memory (CIM) macro is proposed for artificial intelligence accelerations. The CIM macro not only supports simultaneous read + ...
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